The system on glass SOG technology can utilize the fabricating process of amorphous silicon a-Si or the fabricating process of the low temperature poly-silicon LTPS to integrate the system on glass substrate. The LTPS TFT has higher mobility, but the fabricating processes of the LTPS TFT are more complex than that of the a-Si TFT. On the contrary, the mobility of the a-Si TFT is worse than that of the LTPS TFT, but the fabricating processes of the a-Si TFT LCD is simpler and better development than that of the LTPS TFT LCD. Thus, the a-Si TFT has the advantage of low cost.
The a-Si TFT has the restriction of device, such as the threshold voltage Vth of the TFT device gradually increases when a-Si TFT's gate electrode is added bias stress. This is the important reason why the a-Si TFT is not integrated the system on glass (SOG) technology well. Thus, according to the a-Si TFT fabricating process integrated the system on glass (SOG) technology at present, the problem how to solve the unstable of threshold voltage Vth shifting is not easy to overcome.
U.S. Pat. No. 5,222,082, entitled “Shift Register Useful As A Select line Scanner For Liquid Crystal Display” issued on Jun. 22, 1993, discloses a block diagram of a shift register, shown in FIG. 1. The shift register includes a plurality of stages STAGE 1 to STAGE n. Each stage receives the output signal of previous stage in sequence and transmits an output signal OUTPUT 1 to OUTPUT n to the gate lines of the active matrix liquid crystal panel. In the beginning, an input signal INPUT is inputted to the stage 1, and the input signals of other stages are received from the output signal of the previous stage. A clock generator of the shift register circuit provides three clock signals C1, C2 and C3, which can control the odd stage and the even stage of the shift register by using two clock signals of them.
The circuit of the stage 1 is constituted by six TFTs, shown in FIG. 2. Please refer to the time diagram of FIG. 3 simultaneously. The operation of shift register circuit above-mentioned patent is as follows:
When the input signal INPUT and the clock signal C1 are at high voltage level, the TFTs T3 and T4 respectively are turned on and simultaneously a node P2 is designed to be at low voltage level by adjusting the size of two TFTs T3 and T4. When the node P2 is at low voltage level, the TFTs T2 and T6 will be turned off. The TFT T1 is turned on, and thus the voltage level of the node P1 is Vdd minus VthT1 (Vdd−VthT1). The voltage level of the node P1 is still at high voltage level, and thus the TFT T5 will be turned on. Simultaneously, the output signal OUTPUT of an output terminal will be pulled to be at low voltage level by the low voltage level of the clock signal C1.
When the input signal INPUT is at low voltage level, the TFTs T1 and T4 will be turned off. Furthermore, the low voltage level of the clock signal C3 lets the TFT T3 turn off, whereby simultaneously the node P1 is at floating state. Simultaneously, the clock signal C1 is from low voltage level to high voltage level, and thus the node P1 is pulled to be at higher voltage level because of bootstrap effect, such that the high voltage level of the clock signal C1 can perfectly charge to the output terminal OUT. Simultaneously, the node P2 is at the floating state, and the voltage level thereof is decided to still be low voltage level by the previous state. When the input signal INPUT and the clock signals C1 and C3 are at low voltage level, the TFTs T3 and T4 will be turned off. Simultaneously the node P2 will be at the second floating state and still at low voltage level. At next time, if the clock signal C3 from low voltage level to high voltage level, the node P2 will be at high voltage level. Then, the node P2 will be the high voltage level in long time. The node P2 won't be the low voltage level until the input signal INPUT is from low voltage level to high voltage level. For above mentioned, the threshold voltage Vth of TFTs T2 and T6 seriously shifts by adding bias stress of TFT devices.
In conclusion, the disadvantage of U.S. Pat. No. 5,222,082 is that the node P2 of the circuit is at floating state at a short time during a frame time and thus the node P2 may be affected by the clock signals and other noise signals, such that the operation of the circuit is fault. In addition, the TFTs T2 and T6 are stressed by the DC voltage in a long time and thereby threshold voltage Vth of TFT devices seriously shifts. The operation of shift register circuit will fail because of threshold voltage shifting, so the life time reliability and of shift register circuit formed with a-Si TFT must be raised.